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32 Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

Tables 21 through 24 show timing for MAX 9000 devices.

Table 21. MAX 9000 External Timing Characteristics Note (1)

Symbol Parameter Conditions Speed Grade Unit

-10 -15 -20

Min Max Min Max Min Max

PD1

Row I/O pin input to row I/O

pin output

C1 = 35 pF (2) 10.0 15.0 20.0 ns

PD2

Column I/O pin input to

column I/O pin output

C1 = 35 pF

(2)

EPM9320A 10.8 ns

EPM9320 16.0 23.0 ns

EPM9400 16.2 23.2 ns

EPM9480 16.4 23.4 ns

EPM9560A 11.4 ns

EPM9560 16.6 23.6 ns

FSU

Global clock setup time for I/O

cell

3.0 5.0 6.0 ns

Global clock hold time for I/O

cell

0.0 0.0 0.0 ns

FCO

Global clock to I/O cell output

delay

C1 = 35 pF 1.0 (3) 4.8 1.0 (3) 7.0 1.0 (3) 8.5 ns

CNT

Minimum internal global clock

period

(4) 6.9 8.5 10.0 ns

CNT

Maximum internal global clock

frequency

(4) 144.9 117.6 100.0 MHz

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 45 46

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Z Microsystems ZX3 Manual do Utilizador Página 32